[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"project-93271":3},{"id":4,"name":5,"fullName":6,"owner":7,"repo":5,"description":8,"homepage":9,"htmlUrl":9,"language":9,"languages":9,"totalLinesOfCode":9,"stars":10,"forks":11,"watchers":12,"openIssues":13,"contributorsCount":13,"subscribersCount":13,"size":13,"stars1d":13,"stars7d":14,"stars30d":14,"stars90d":13,"forks30d":13,"starsTrendScore":13,"compositeScore":15,"rankGlobal":9,"rankLanguage":9,"license":9,"archived":16,"fork":16,"defaultBranch":17,"hasWiki":18,"hasPages":16,"topics":19,"createdAt":9,"pushedAt":9,"updatedAt":20,"readmeContent":21,"aiSummary":22,"trendingCount":13,"starSnapshotCount":13,"syncStatus":23,"lastSyncTime":24,"discoverSource":25},93271,"awesome-ai-accelerators","LonghornSilicon\u002Fawesome-ai-accelerators","LonghornSilicon","A curated list of AI accelerator papers, resources, tools, and open-source projects.",null,126,13,1,0,17,50.64,false,"main",true,[],"2026-07-22 04:02:08","\u003Cdiv align=\"center\">\n\n# Awesome AI Accelerators [![Awesome](https:\u002F\u002Fawesome.re\u002Fbadge.svg)](https:\u002F\u002Fawesome.re)\n\n> A curated list of papers, tools, and resources for **AI accelerators** — spanning the entire stack from silicon to serving systems.\n\n[![PRs Welcome](https:\u002F\u002Fimg.shields.io\u002Fbadge\u002FPRs-welcome-brightgreen.svg)](CONTRIBUTING.md)\n[![License: CC0-1.0](https:\u002F\u002Fimg.shields.io\u002Fbadge\u002FLicense-CC0%201.0-lightgrey.svg)](LICENSE)\n\n\u003C\u002Fdiv>\n\nAI accelerators are the engines behind modern machine learning — the GPUs, TPUs, NPUs, and custom ASICs that make training and inference practical at scale. Building and programming them is a deeply interdisciplinary craft that spans deep learning, computer architecture, compilers, GPU programming, RTL design, and physical implementation.\n\nThis list is a **curated, opinionated map** of that landscape. It favors canonical papers and widely adopted open-source projects over exhaustive coverage. Whether you are an undergraduate taking your first architecture course, a PhD student researching dataflow architectures, or an engineer optimizing kernels at a frontier lab, the goal is to give you the best resource for each topic — and a clear path through the rest.\n\n---\n\n## Contents\n\n- [AI Foundations](#ai-foundations)\n  - [AI Fundamentals](#ai-fundamentals)\n  - [Deep Learning](#deep-learning)\n  - [Transformers & LLMs](#transformers--llms)\n  - [Diffusion Models](#diffusion-models)\n  - [Vision Models](#vision-models)\n  - [Reinforcement Learning](#reinforcement-learning)\n- [AI Inference](#ai-inference)\n  - [Quantization](#quantization)\n  - [KV Cache](#kv-cache)\n  - [Speculative Decoding](#speculative-decoding)\n  - [Prefix Caching](#prefix-caching)\n  - [Continuous Batching](#continuous-batching)\n  - [Mixture of Experts](#mixture-of-experts)\n  - [Sparsity & Pruning](#sparsity--pruning)\n  - [Scheduling](#scheduling)\n  - [Memory Optimization](#memory-optimization)\n  - [Serving Systems](#serving-systems)\n- [GPU Programming](#gpu-programming)\n  - [CUDA](#cuda)\n  - [Triton](#triton)\n  - [ROCm](#rocm)\n  - [Metal](#metal)\n- [AI Kernels](#ai-kernels)\n  - [GEMM](#gemm)\n  - [FlashAttention](#flashattention)\n  - [PagedAttention](#pagedattention)\n  - [Normalization & Softmax](#normalization--softmax)\n  - [RoPE & Positional Encodings](#rope--positional-encodings)\n  - [Fused Operators](#fused-operators)\n  - [Kernel Optimization Guides](#kernel-optimization-guides)\n- [Runtime Systems](#runtime-systems)\n- [Compilers](#compilers)\n- [Computer Architecture](#computer-architecture)\n  - [Foundations](#foundations)\n  - [Memory Systems & Cache](#memory-systems--cache)\n  - [Interconnect & NoC](#interconnect--noc)\n  - [Dataflow & Systolic Arrays](#dataflow--systolic-arrays)\n  - [SIMD, SIMT & Tensor Cores](#simd-simt--tensor-cores)\n  - [Processing-in-Memory](#processing-in-memory)\n- [AI Accelerator Architecture](#ai-accelerator-architecture)\n  - [GPUs](#gpus)\n  - [TPUs & Systolic ASICs](#tpus--systolic-asics)\n  - [NPUs & Edge AI](#npus--edge-ai)\n  - [FPGA & Reconfigurable](#fpga--reconfigurable)\n  - [RISC-V for AI](#risc-v-for-ai)\n- [Simulators & Modeling](#simulators--modeling)\n- [Chip Design](#chip-design)\n  - [Blogs & Newsletters](#blogs--newsletters)\n  - [YouTube Channels](#youtube-channels)\n  - [Interactive & Visual](#interactive--visual)\n- [RTL Design](#rtl-design)\n- [Design Verification](#design-verification)\n- [Physical Design](#physical-design)\n- [University Courses](#university-courses)\n\n---\n\n## AI Foundations\n\nUnderstanding the workloads is the prerequisite for accelerating them. This section covers the models that drive accelerator design.\n\n### AI Fundamentals\n\n- [Deep Learning](https:\u002F\u002Fwww.deeplearningbook.org\u002F) — Goodfellow, Bengio, and Courville's foundational textbook, freely available online.\n- [Dive into Deep Learning (D2L)](https:\u002F\u002Fd2l.ai\u002F) — Interactive book with runnable code in PyTorch, JAX, and TensorFlow.\n- [Neural Networks and Deep Learning](http:\u002F\u002Fneuralnetworksanddeeplearning.com\u002F) — Michael Nielsen's intuitive introduction to the core ideas.\n- [The Matrix Calculus You Need For Deep Learning](https:\u002F\u002Fexplained.ai\u002Fmatrix-calculus\u002F) — Parr and Howard's practical primer on the math behind backprop.\n\n### Deep Learning\n\n- [ImageNet Classification with Deep CNNs (AlexNet)](https:\u002F\u002Fproceedings.neurips.cc\u002Fpaper\u002F2012\u002Fhash\u002Fc399862d3b9d6b76c8436e924a68c45b-Abstract.html) — The 2012 paper that ignited the deep learning era.\n- [Deep Residual Learning (ResNet)](https:\u002F\u002Farxiv.org\u002Fabs\u002F1512.03385) — Residual connections that enabled very deep networks.\n- [Batch Normalization](https:\u002F\u002Farxiv.org\u002Fabs\u002F1502.03167) — Normalizing activations to accelerate and stabilize training.\n- [Adam: A Method for Stochastic Optimization](https:\u002F\u002Farxiv.org\u002Fabs\u002F1412.6980) — The default optimizer for most deep learning workloads.\n- [The Bitter Lesson](http:\u002F\u002Fwww.incompleteideas.net\u002FIncIdeas\u002FBitterLesson.html) — Rich Sutton's essay on why general methods that scale with compute win.\n\n### Transformers & LLMs\n\n- [Attention Is All You Need](https:\u002F\u002Farxiv.org\u002Fabs\u002F1706.03762) — The Transformer architecture; the single most important paper for modern AI accelerators.\n- [The Illustrated Transformer](https:\u002F\u002Fjalammar.github.io\u002Fillustrated-transformer\u002F) — Jay Alammar's visual walkthrough of the architecture.\n- [The Annotated Transformer](https:\u002F\u002Fnlp.seas.harvard.edu\u002Fannotated-transformer\u002F) — Harvard NLP's line-by-line implementation in PyTorch.\n- [BERT](https:\u002F\u002Farxiv.org\u002Fabs\u002F1810.04805) — Bidirectional pretraining that reshaped NLP.\n- [GPT-2: Language Models are Unsupervised Multitask Learners](https:\u002F\u002Fcdn.openai.com\u002Fbetter-language-models\u002Flanguage_models_are_unsupervised_multitask_learners.pdf) — Scaling generative pretraining toward zero-shot task transfer.\n- [GPT-3: Language Models are Few-Shot Learners](https:\u002F\u002Farxiv.org\u002Fabs\u002F2005.14165) — Demonstrated emergent in-context learning at scale.\n- [T5: Exploring the Limits of Transfer Learning](https:\u002F\u002Farxiv.org\u002Fabs\u002F1910.10683) — The unified text-to-text framing of NLP tasks.\n- [Scaling Laws for Neural Language Models](https:\u002F\u002Farxiv.org\u002Fabs\u002F2001.08361) — Kaplan et al.'s power-law relationships between compute, data, and loss.\n- [Training Compute-Optimal LLMs (Chinchilla)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2203.15556) — The compute-optimal scaling result that reset training recipes.\n- [LLaMA](https:\u002F\u002Farxiv.org\u002Fabs\u002F2302.13971) — Efficient open foundation models that catalyzed the open LLM ecosystem.\n- [Mistral 7B](https:\u002F\u002Farxiv.org\u002Fabs\u002F2310.06825) — Grouped-query and sliding-window attention for efficient inference.\n- [DeepSeek-V3](https:\u002F\u002Farxiv.org\u002Fabs\u002F2412.19437) — A 671B fine-grained MoE model trained efficiently with FP8 and MLA.\n- [DeepSeek-R1](https:\u002F\u002Farxiv.org\u002Fabs\u002F2501.12948) — Eliciting strong reasoning through large-scale reinforcement learning.\n- [nanoGPT](https:\u002F\u002Fgithub.com\u002Fkarpathy\u002FnanoGPT) — Karpathy's minimal, hackable GPT training and inference codebase.\n- [The Ultra-Scale Playbook](https:\u002F\u002Fhuggingface.co\u002Fspaces\u002Fnanotron\u002Fultrascale-playbook) — Hugging Face's practical guide to training LLMs on GPU clusters (data, tensor, pipeline, and expert parallelism).\n- [The Smol Training Playbook](https:\u002F\u002Fhuggingface.co\u002Fspaces\u002FHuggingFaceTB\u002Fsmol-training-playbook) — Hugging Face's end-to-end field guide to building world-class LLMs.\n\n### Diffusion Models\n\n- [Denoising Diffusion Probabilistic Models (DDPM)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2006.11239) — The paper that made diffusion models practical.\n- [High-Resolution Image Synthesis with Latent Diffusion (Stable Diffusion)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2112.10752) — Diffusion in latent space for efficient, high-quality generation.\n- [Classifier-Free Diffusion Guidance](https:\u002F\u002Farxiv.org\u002Fabs\u002F2207.12598) — The guidance technique underlying modern text-to-image models.\n- [Scalable Diffusion Models with Transformers (DiT)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2212.09748) — Replacing the U-Net backbone with transformers.\n- [What are Diffusion Models?](https:\u002F\u002Flilianweng.github.io\u002Fposts\u002F2021-07-11-diffusion-models\u002F) — Lilian Weng's comprehensive tutorial.\n\n### Vision Models\n\n- [An Image is Worth 16x16 Words (ViT)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2010.11929) — Applying pure transformers to image classification.\n- [Segment Anything (SAM)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2304.02643) — A promptable foundation model for image segmentation.\n- [CLIP: Learning Transferable Visual Models](https:\u002F\u002Farxiv.org\u002Fabs\u002F2103.00020) — Contrastive language-image pretraining that bridges vision and text.\n- [YOLO](https:\u002F\u002Farxiv.org\u002Fabs\u002F1506.02640) — Real-time object detection as a single regression problem.\n\n### Reinforcement Learning\n\n- [Reinforcement Learning: An Introduction](http:\u002F\u002Fincompleteideas.net\u002Fbook\u002Fthe-book.html) — Sutton and Barto's canonical textbook, freely available.\n- [Playing Atari with Deep RL (DQN)](https:\u002F\u002Farxiv.org\u002Fabs\u002F1312.5602) — Deep Q-networks that learned to play from pixels.\n- [Proximal Policy Optimization (PPO)](https:\u002F\u002Farxiv.org\u002Fabs\u002F1707.06347) — The workhorse policy-gradient algorithm, now central to RLHF.\n- [Spinning Up in Deep RL](https:\u002F\u002Fspinningup.openai.com\u002F) — OpenAI's educational resource with clean implementations.\n\n---\n\n## AI Inference\n\nInference — not training — dominates the lifetime compute of a deployed model. This section covers the algorithms and systems that make LLM serving fast and cheap.\n\n### Quantization\n\n- [TurboQuant](https:\u002F\u002Farxiv.org\u002Fabs\u002F2504.19874) — Online vector quantization with near-optimal distortion, delivering large KV cache memory savings and attention speedups.\n- [LLM.int8()](https:\u002F\u002Farxiv.org\u002Fabs\u002F2208.07339) — 8-bit matrix multiplication for transformers with outlier handling.\n- [GPTQ](https:\u002F\u002Farxiv.org\u002Fabs\u002F2210.17323) — Accurate post-training quantization to 3–4 bits.\n- [AWQ: Activation-aware Weight Quantization](https:\u002F\u002Farxiv.org\u002Fabs\u002F2306.00978) — Protecting salient weights for low-bit LLM inference.\n- [SmoothQuant](https:\u002F\u002Farxiv.org\u002Fabs\u002F2211.10438) — Migrating quantization difficulty from activations to weights.\n- [QLoRA](https:\u002F\u002Farxiv.org\u002Fabs\u002F2305.14314) — 4-bit NormalFloat quantization enabling fine-tuning on a single GPU.\n- [FP8 Formats for Deep Learning](https:\u002F\u002Farxiv.org\u002Fabs\u002F2209.05433) — The NVIDIA\u002FArm\u002FIntel proposal behind Hopper's FP8 support.\n- [A Survey of Quantization Methods](https:\u002F\u002Farxiv.org\u002Fabs\u002F2103.13630) — Comprehensive survey of efficient neural network inference.\n\n### KV Cache\n\n- [Efficient Memory Management for LLM Serving (PagedAttention)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2309.06180) — The vLLM paper; treats KV cache like OS virtual memory.\n- [Multi-Query Attention](https:\u002F\u002Farxiv.org\u002Fabs\u002F1911.02150) — Sharing keys and values across heads to shrink the KV cache.\n- [GQA: Grouped-Query Attention](https:\u002F\u002Farxiv.org\u002Fabs\u002F2305.13245) — Interpolating between multi-head and multi-query attention.\n- [H2O: Heavy-Hitter Oracle](https:\u002F\u002Farxiv.org\u002Fabs\u002F2306.14048) — KV cache eviction based on attention scores.\n- [KVQuant](https:\u002F\u002Farxiv.org\u002Fabs\u002F2401.18079) — Ultra-low-bit KV cache quantization for long context.\n- [DeepSeek-V2 (Multi-head Latent Attention)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2405.04434) — Low-rank KV compression that dramatically cuts cache size.\n\n### Speculative Decoding\n\n- [Fast Inference from Transformers via Speculative Decoding](https:\u002F\u002Farxiv.org\u002Fabs\u002F2211.17192) — The original speculative decoding paper from Google.\n- [Accelerating LLM Decoding with Speculative Sampling](https:\u002F\u002Farxiv.org\u002Fabs\u002F2302.01318) — DeepMind's concurrent formulation.\n- [Medusa](https:\u002F\u002Farxiv.org\u002Fabs\u002F2401.10774) — Multiple decoding heads for parallel speculation without a draft model.\n- [EAGLE](https:\u002F\u002Farxiv.org\u002Fabs\u002F2401.15077) — Speculative sampling at the feature level for higher acceptance rates.\n- [Lookahead Decoding](https:\u002F\u002Farxiv.org\u002Fabs\u002F2402.02057) — Breaking the sequential dependency without a draft model.\n\n### Prefix Caching\n\n- [SGLang: Efficient Execution with RadixAttention](https:\u002F\u002Farxiv.org\u002Fabs\u002F2312.07104) — Automatic KV reuse across requests via a radix tree.\n- [Prompt Cache](https:\u002F\u002Farxiv.org\u002Fabs\u002F2311.04934) — Modular attention reuse for recurring text segments.\n- [ChunkAttention](https:\u002F\u002Farxiv.org\u002Fabs\u002F2402.15220) — Prefix-aware KV cache with a shared prefix trie.\n\n### Continuous Batching\n\n- [Orca: A Distributed Serving System for Transformers](https:\u002F\u002Fwww.usenix.org\u002Fconference\u002Fosdi22\u002Fpresentation\u002Fyu) — Introduced iteration-level (continuous) batching at OSDI '22.\n- [How Continuous Batching Enables 23x Throughput](https:\u002F\u002Fwww.anyscale.com\u002Fblog\u002Fcontinuous-batching-llm-inference) — Anyscale's widely cited explainer.\n- [DistServe](https:\u002F\u002Farxiv.org\u002Fabs\u002F2401.09670) — Disaggregating prefill and decode for goodput-optimal serving.\n- [Sarathi-Serve](https:\u002F\u002Farxiv.org\u002Fabs\u002F2403.02310) — Chunked prefills that balance throughput and latency.\n\n### Mixture of Experts\n\n- [Outrageously Large Neural Networks (Sparsely-Gated MoE)](https:\u002F\u002Farxiv.org\u002Fabs\u002F1701.06538) — Shazeer et al.'s foundational MoE layer.\n- [Switch Transformers](https:\u002F\u002Farxiv.org\u002Fabs\u002F2101.03961) — Simplified routing scaling to trillion-parameter models.\n- [GShard](https:\u002F\u002Farxiv.org\u002Fabs\u002F2006.16668) — Scaling MoE with automatic sharding.\n- [Mixtral of Experts](https:\u002F\u002Farxiv.org\u002Fabs\u002F2401.04088) — A strong open sparse MoE model.\n- [MegaBlocks](https:\u002F\u002Farxiv.org\u002Fabs\u002F2211.15841) — Block-sparse GPU kernels for dropless MoE training.\n- [DeepSeek-V3](https:\u002F\u002Farxiv.org\u002Fabs\u002F2412.19437) — Fine-grained MoE with auxiliary-loss-free load balancing at scale.\n\n### Sparsity & Pruning\n\n- [The Lottery Ticket Hypothesis](https:\u002F\u002Farxiv.org\u002Fabs\u002F1803.03635) — Sparse subnetworks that train to full accuracy.\n- [Learning both Weights and Connections (Deep Compression)](https:\u002F\u002Farxiv.org\u002Fabs\u002F1506.02626) — Han et al.'s pruning + quantization + Huffman coding pipeline.\n- [SparseGPT](https:\u002F\u002Farxiv.org\u002Fabs\u002F2301.00774) — One-shot pruning of massive language models.\n- [Wanda](https:\u002F\u002Farxiv.org\u002Fabs\u002F2306.11695) — Pruning by weights and activations, no retraining required.\n- [Accelerating Sparse DNNs with 2:4 Sparsity](https:\u002F\u002Farxiv.org\u002Fabs\u002F2104.08378) — NVIDIA's structured sparsity for Tensor Cores.\n\n### Scheduling\n\n- [FastServe](https:\u002F\u002Farxiv.org\u002Fabs\u002F2305.05920) — Preemptive scheduling to minimize job completion time.\n- [Llumnix](https:\u002F\u002Farxiv.org\u002Fabs\u002F2406.03243) — Dynamic request rescheduling across serving instances.\n- [Splitwise](https:\u002F\u002Farxiv.org\u002Fabs\u002F2311.18677) — Phase-splitting prefill and decode across heterogeneous hardware.\n\n### Memory Optimization\n\n- [ZeRO: Memory Optimizations Toward Training Trillion-Parameter Models](https:\u002F\u002Farxiv.org\u002Fabs\u002F1910.02054) — Partitioning optimizer state, gradients, and parameters.\n- [FlexGen](https:\u002F\u002Farxiv.org\u002Fabs\u002F2303.06865) — High-throughput generative inference with offloading on a single GPU.\n- [Reducing Activation Recomputation (Selective Checkpointing)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2205.05198) — Trading compute for memory in large transformers.\n- [InfiniGen](https:\u002F\u002Farxiv.org\u002Fabs\u002F2406.19707) — Dynamic KV cache management with speculative prefetching.\n\n### Serving Systems\n\n- [DeepSpeed-Inference](https:\u002F\u002Farxiv.org\u002Fabs\u002F2207.00032) — Multi-GPU inference optimizations for transformer models.\n- [AlpaServe](https:\u002F\u002Farxiv.org\u002Fabs\u002F2302.11665) — Statistical multiplexing with model parallelism for serving.\n- [Efficiently Scaling Transformer Inference](https:\u002F\u002Farxiv.org\u002Fabs\u002F2211.05102) — Google's partitioning analysis for TPU inference at scale.\n- [Mooncake](https:\u002F\u002Farxiv.org\u002Fabs\u002F2407.00079) — KVCache-centric disaggregated architecture behind Kimi.\n\n---\n\n## GPU Programming\n\nThe lingua franca of accelerator programming. This section covers the major parallel programming models.\n\n### CUDA\n\n- [CUDA C++ Programming Guide](https:\u002F\u002Fdocs.nvidia.com\u002Fcuda\u002Fcuda-c-programming-guide\u002F) — The authoritative reference from NVIDIA.\n- [CUDA C++ Best Practices Guide](https:\u002F\u002Fdocs.nvidia.com\u002Fcuda\u002Fcuda-c-best-practices-guide\u002F) — Performance optimization guidance straight from the source.\n- [Programming Massively Parallel Processors](https:\u002F\u002Fwww.elsevier.com\u002Fbooks\u002Fprogramming-massively-parallel-processors\u002Fhwu\u002F978-0-323-91231-0) — Hwu, Kirk, and El Hajj's definitive CUDA textbook (PMPP).\n- [How to Optimize a CUDA Matmul Kernel](https:\u002F\u002Fsiboehm.com\u002Farticles\u002F22\u002FCUDA-MMM) — Simon Boehm's step-by-step walk to near-cuBLAS performance.\n- [GPU MODE Lectures](https:\u002F\u002Fgithub.com\u002Fgpu-mode\u002Flectures) — Community lecture series and code on writing fast GPU kernels.\n- [CUTLASS](https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fcutlass) — NVIDIA's CUDA templates for high-performance GEMM and beyond.\n\n### Triton\n\n- [Triton: An Intermediate Language and Compiler](https:\u002F\u002Fwww.eecs.harvard.edu\u002F~htk\u002Fpublication\u002F2019-mapl-tillet-kung-cox.pdf) — The original paper by Philippe Tillet.\n- [Triton](https:\u002F\u002Fgithub.com\u002Ftriton-lang\u002Ftriton) — OpenAI's Python DSL for writing efficient GPU kernels.\n- [Triton Tutorials](https:\u002F\u002Ftriton-lang.org\u002Fmain\u002Fgetting-started\u002Ftutorials\u002Findex.html) — Official tutorials from vector-add to fused attention.\n\n### ROCm\n\n- [ROCm Documentation](https:\u002F\u002Frocm.docs.amd.com\u002F) — AMD's open compute platform for GPU acceleration.\n- [HIP Programming Guide](https:\u002F\u002Frocm.docs.amd.com\u002Fprojects\u002FHIP\u002F) — CUDA-portable C++ runtime API for AMD and NVIDIA GPUs.\n- [Composable Kernel](https:\u002F\u002Fgithub.com\u002FROCm\u002Fcomposable_kernel) — AMD's performance library for GEMM and fused operators.\n\n### Metal\n\n- [Metal Performance Shaders](https:\u002F\u002Fdeveloper.apple.com\u002Fdocumentation\u002Fmetalperformanceshaders) — Apple's optimized GPU compute primitives.\n- [MLX](https:\u002F\u002Fgithub.com\u002Fml-explore\u002Fmlx) — Apple's NumPy-like array framework for Apple silicon.\n- [Metal Shading Language Specification](https:\u002F\u002Fdeveloper.apple.com\u002Fmetal\u002FMetal-Shading-Language-Specification.pdf) — The reference for writing Metal compute kernels.\n\n---\n\n## AI Kernels\n\nThe hand-tuned building blocks where most accelerator FLOPs are spent.\n\n### GEMM\n\n- [Anatomy of High-Performance Matrix Multiplication](https:\u002F\u002Fwww.cs.utexas.edu\u002F~flame\u002Fpubs\u002FGotoTOMS_revision.pdf) — Goto and van de Geijn's classic on blocking for the memory hierarchy.\n- [CUTLASS](https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fcutlass) — Composable GEMM templates that expose Tensor Core performance.\n- [How To Optimize GEMM](https:\u002F\u002Fgithub.com\u002Fflame\u002Fhow-to-optimize-gemm) — A pedagogical, step-by-step optimization of matrix multiply.\n- [CuTe Layout Algebra](https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fcutlass\u002Fblob\u002Fmain\u002Fmedia\u002Fdocs\u002Fcute\u002F00_quickstart.md) — CUTLASS 3.x's abstraction for tensor layouts and tiling.\n\n### FlashAttention\n\n- [FlashAttention](https:\u002F\u002Farxiv.org\u002Fabs\u002F2205.14135) — IO-aware exact attention that avoids materializing the score matrix.\n- [FlashAttention-2](https:\u002F\u002Farxiv.org\u002Fabs\u002F2307.08691) — Better parallelism and work partitioning for near-peak throughput.\n- [FlashAttention-3](https:\u002F\u002Farxiv.org\u002Fabs\u002F2407.08608) — Exploiting Hopper asynchrony and FP8 for the H100.\n- [flash-attention](https:\u002F\u002Fgithub.com\u002FDao-AILab\u002Fflash-attention) — The reference implementation from Tri Dao's lab.\n- [FlashInfer](https:\u002F\u002Fgithub.com\u002Fflashinfer-ai\u002Fflashinfer) — A kernel library for LLM serving with attention variants.\n\n### PagedAttention\n\n- [PagedAttention (vLLM)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2309.06180) — Non-contiguous KV cache blocks to eliminate memory fragmentation.\n- [vLLM Kernels](https:\u002F\u002Fgithub.com\u002Fvllm-project\u002Fvllm\u002Ftree\u002Fmain\u002Fcsrc) — Production PagedAttention and quantized kernel implementations.\n\n### Normalization & Softmax\n\n- [Root Mean Square Layer Normalization](https:\u002F\u002Farxiv.org\u002Fabs\u002F1910.07467) — RMSNorm, the normalization used in most modern LLMs.\n- [Layer Normalization](https:\u002F\u002Farxiv.org\u002Fabs\u002F1607.06450) — Ba, Kiros, and Hinton's original formulation.\n- [Online Normalizer Calculation for Softmax](https:\u002F\u002Farxiv.org\u002Fabs\u002F1805.02867) — The single-pass softmax trick underlying FlashAttention.\n\n### RoPE & Positional Encodings\n\n- [RoFormer: Rotary Position Embedding](https:\u002F\u002Farxiv.org\u002Fabs\u002F2104.09864) — RoPE, the positional encoding used across modern LLMs.\n- [YaRN](https:\u002F\u002Farxiv.org\u002Fabs\u002F2309.00071) — Efficient context-window extension for RoPE models.\n- [ALiBi](https:\u002F\u002Farxiv.org\u002Fabs\u002F2108.12409) — Attention with linear biases for length extrapolation.\n\n### Fused Operators\n\n- [Automatic Kernel Fusion (TVM)](https:\u002F\u002Farxiv.org\u002Fabs\u002F1802.04799) — Operator fusion as part of an end-to-end DL compiler.\n- [Liger Kernel](https:\u002F\u002Fgithub.com\u002Flinkedin\u002FLiger-Kernel) — Fused Triton kernels for efficient LLM training.\n- [NVIDIA Apex](https:\u002F\u002Fgithub.com\u002FNVIDIA\u002Fapex) — Fused Adam, LayerNorm, and other mixed-precision training kernels.\n\n### Kernel Optimization Guides\n\n- [GPU Performance Background](https:\u002F\u002Fdocs.nvidia.com\u002Fdeeplearning\u002Fperformance\u002Fdl-performance-gpu-background\u002Findex.html) — NVIDIA's model for reasoning about arithmetic intensity and roofline.\n- [Making Deep Learning Go Brrrr From First Principles](https:\u002F\u002Fhorace.io\u002Fbrrr_intro.html) — Horace He on compute, memory, and overhead bound regimes.\n- [What Every Programmer Should Know About Memory](https:\u002F\u002Fwww.akkadia.org\u002Fdrepper\u002Fcpumemory.pdf) — Ulrich Drepper's essential treatment of the memory hierarchy.\n\n---\n\n## Runtime Systems\n\nFrameworks that take a trained model and run it efficiently on real hardware.\n\n- [vLLM](https:\u002F\u002Fgithub.com\u002Fvllm-project\u002Fvllm) — High-throughput LLM serving engine built around PagedAttention.\n- [TensorRT-LLM](https:\u002F\u002Fgithub.com\u002FNVIDIA\u002FTensorRT-LLM) — NVIDIA's optimized LLM inference library with in-flight batching.\n- [SGLang](https:\u002F\u002Fgithub.com\u002Fsgl-project\u002Fsglang) — Fast serving with RadixAttention and a co-designed frontend language.\n- [MLC-LLM](https:\u002F\u002Fgithub.com\u002Fmlc-ai\u002Fmlc-llm) — Universal LLM deployment across GPUs, phones, and browsers via TVM.\n- [llama.cpp](https:\u002F\u002Fgithub.com\u002Fggml-org\u002Fllama.cpp) — Portable C\u002FC++ inference with aggressive quantization (GGUF).\n- [Ollama](https:\u002F\u002Fgithub.com\u002Follama\u002Follama) — Simple local model running built on llama.cpp.\n- [TensorRT](https:\u002F\u002Fgithub.com\u002FNVIDIA\u002FTensorRT) — NVIDIA's high-performance deep learning inference SDK.\n- [ONNX Runtime](https:\u002F\u002Fgithub.com\u002Fmicrosoft\u002Fonnxruntime) — Cross-platform inference and training accelerator.\n- [Apache TVM](https:\u002F\u002Fgithub.com\u002Fapache\u002Ftvm) — End-to-end deep learning compiler stack (see [Compilers](#compilers)).\n- [tinygrad](https:\u002F\u002Fgithub.com\u002Ftinygrad\u002Ftinygrad) — A minimalist framework with a lazy, fused execution model.\n- [ExecuTorch](https:\u002F\u002Fgithub.com\u002Fpytorch\u002Fexecutorch) — PyTorch's on-device inference runtime for mobile and edge.\n- [OpenXLA \u002F XLA](https:\u002F\u002Fgithub.com\u002Fopenxla\u002Fxla) — The domain-specific compiler behind JAX and TensorFlow.\n- [DeepSpeed](https:\u002F\u002Fgithub.com\u002Fmicrosoft\u002FDeepSpeed) — Microsoft's training and inference optimization library.\n- [LMDeploy](https:\u002F\u002Fgithub.com\u002FInternLM\u002Flmdeploy) — Toolkit for compressing and serving LLMs.\n- [Text Generation Inference (TGI)](https:\u002F\u002Fgithub.com\u002Fhuggingface\u002Ftext-generation-inference) — Hugging Face's production serving toolkit.\n\n---\n\n## Compilers\n\nThe bridge between ML frameworks and silicon.\n\n- [MLIR](https:\u002F\u002Fmlir.llvm.org\u002F) — Multi-Level IR; the shared compiler infrastructure behind most modern AI stacks.\n- [MLIR: Scaling Compiler Infrastructure (paper)](https:\u002F\u002Farxiv.org\u002Fabs\u002F2002.11054) — Lattner et al.'s introduction to the framework.\n- [LLVM](https:\u002F\u002Fllvm.org\u002F) — The compiler infrastructure that underpins essentially everything below.\n- [TVM: An Automated End-to-End Optimizing Compiler](https:\u002F\u002Fwww.usenix.org\u002Fconference\u002Fosdi18\u002Fpresentation\u002Fchen) — The Apache TVM paper.\n- [IREE](https:\u002F\u002Fgithub.com\u002Firee-org\u002Firee) — An MLIR-based end-to-end compiler and runtime for ML models.\n- [OpenXLA](https:\u002F\u002Fgithub.com\u002Fopenxla\u002Fxla) — XLA and StableHLO, the compiler ecosystem for JAX\u002FTF\u002FPyTorch.\n- [Triton Compiler](https:\u002F\u002Fgithub.com\u002Ftriton-lang\u002Ftriton) — Lowers a Python tile DSL to fast GPU code through MLIR.\n- [torch.compile \u002F TorchInductor](https:\u002F\u002Fpytorch.org\u002Fget-started\u002Fpytorch-2.0\u002F) — PyTorch 2.x's graph capture and Triton-based codegen.\n- [Glow](https:\u002F\u002Fgithub.com\u002Fpytorch\u002Fglow) — A graph-lowering compiler for neural network hardware accelerators.\n- [Mojo](https:\u002F\u002Fwww.modular.com\u002Fmojo) — Modular's Python-superset language for AI systems programming.\n- [Halide](https:\u002F\u002Fhalide-lang.org\u002F) — Decoupling algorithm from schedule for high-performance tensor and imaging code.\n- [The Deep Learning Compiler: A Comprehensive Survey](https:\u002F\u002Farxiv.org\u002Fabs\u002F2002.03794) — A map of the DL compiler landscape.\n\n---\n\n## Computer Architecture\n\nThe foundation every accelerator is built on.\n\n### Foundations\n\n- [Computer Architecture: A Quantitative Approach](https:\u002F\u002Fwww.elsevier.com\u002Fbooks\u002Fcomputer-architecture\u002Fhennessy\u002F978-0-12-811905-1) — Hennessy and Patterson's definitive graduate text.\n- [Computer Organization and Design](https:\u002F\u002Fwww.elsevier.com\u002Fbooks\u002Fcomputer-organization-and-design-risc-v-edition\u002Fpatterson\u002F978-0-12-820331-6) — Patterson and Hennessy's undergraduate RISC-V edition.\n- [Processor Microarchitecture: An Implementation Perspective](https:\u002F\u002Fdl.icdst.org\u002Fpdfs\u002Ffiles\u002F15b09def448c317556dc0fc412aee571.pdf) — González, Latorre, and Magklis's concise tour of how out-of-order cores are actually built.\n- [A New Golden Age for Computer Architecture](https:\u002F\u002Fcacm.acm.org\u002Fmagazines\u002F2019\u002F2\u002F234352-a-new-golden-age-for-computer-architecture\u002Ffulltext) — Hennessy and Patterson's Turing Award lecture on domain-specific architectures.\n- [Onur Mutlu's Computer Architecture Lectures](https:\u002F\u002Fsafari.ethz.ch\u002Farchitecture\u002F) — ETH Zürich's comprehensive, freely available course.\n\n### Memory Systems & Cache\n\n- [What Every Programmer Should Know About Memory](https:\u002F\u002Fwww.akkadia.org\u002Fdrepper\u002Fcpumemory.pdf) — The reference on caches, DRAM, and memory-aware programming.\n- [High Bandwidth Memory (HBM) Standard](https:\u002F\u002Fwww.jedec.org\u002Fstandards-documents\u002Fdocs\u002Fjesd235a) — The JEDEC standard powering modern accelerator memory.\n- [DRAMSim3](https:\u002F\u002Fgithub.com\u002Fumd-memsys\u002FDRAMsim3) — A cycle-accurate DRAM simulator for architecture research.\n- [Ramulator 2.0](https:\u002F\u002Fgithub.com\u002FCMU-SAFARI\u002Framulator2) — A fast, extensible DRAM simulator for modern memory standards.\n\n### Interconnect & NoC\n\n- [Principles and Practices of Interconnection Networks](https:\u002F\u002Fwww.elsevier.com\u002Fbooks\u002Fprinciples-and-practices-of-interconnection-networks\u002Fdally\u002F978-0-12-200751-4) — Dally and Towles's definitive text.\n- [NVLink and NVSwitch](https:\u002F\u002Fwww.nvidia.com\u002Fen-us\u002Fdata-center\u002Fnvlink\u002F) — NVIDIA's high-bandwidth GPU-to-GPU interconnect.\n- [BookSim2](https:\u002F\u002Fgithub.com\u002Fbooksim\u002Fbooksim2) — A cycle-accurate interconnection network simulator.\n- [Ultra Ethernet Consortium](https:\u002F\u002Fultraethernet.org\u002F) — An emerging open standard for scale-out AI fabrics.\n\n### Dataflow & Systolic Arrays\n\n- [Why Systolic Architectures?](https:\u002F\u002Fwww.eecs.harvard.edu\u002F~htk\u002Fpublication\u002F1982-kung-why-systolic-architecture.pdf) — H. T. Kung and Charles Leiserson's foundational 1982 work.\n- [Eyeriss: Energy-Efficient Reconfigurable Accelerator](https:\u002F\u002Fieeexplore.ieee.org\u002Fdocument\u002F7738524) — Chen et al.'s influential dataflow accelerator and taxonomy.\n- [Efficient Processing of Deep Neural Networks](https:\u002F\u002Flink.springer.com\u002Fbook\u002F10.1007\u002F978-3-031-01766-7) — Sze, Chen, Yang, and Emer's essential survey book.\n- [Timeloop \u002F Accelergy](https:\u002F\u002Fgithub.com\u002FNVlabs\u002Ftimeloop) — Infrastructure for evaluating and mapping DNN accelerator dataflows.\n- [MAESTRO](https:\u002F\u002Fgithub.com\u002Fmaestro-project\u002Fmaestro) — An analytical cost model for DNN dataflows.\n\n### SIMD, SIMT & Tensor Cores\n\n- [Volta Architecture Whitepaper](https:\u002F\u002Fimages.nvidia.com\u002Fcontent\u002Fvolta-architecture\u002Fpdf\u002Fvolta-architecture-whitepaper.pdf) — The introduction of Tensor Cores.\n- [Dissecting the NVIDIA Volta GPU via Microbenchmarking](https:\u002F\u002Farxiv.org\u002Fabs\u002F1804.06826) — A detailed reverse-engineering of Tensor Core behavior.\n- [Dissecting Tensor Cores via Microbenchmarks](https:\u002F\u002Farxiv.org\u002Fabs\u002F2206.02874) — Programmability, performance, and precision across generations.\n- [Modal GPU Glossary](https:\u002F\u002Fmodal.com\u002Fgpu-glossary) — A clear reference for SIMT execution and GPU terminology.\n\n### Processing-in-Memory\n\n- [A Modern Primer on Processing in Memory](https:\u002F\u002Farxiv.org\u002Fabs\u002F2012.03112) — Mutlu et al.'s comprehensive introduction to PIM.\n- [PRIME: A Novel PIM Architecture for Neural Network Computation](https:\u002F\u002Fieeexplore.ieee.org\u002Fdocument\u002F7551380) — ReRAM-based neural network acceleration in memory.\n- [Samsung HBM-PIM (Aquabolt-XL)](https:\u002F\u002Fieeexplore.ieee.org\u002Fdocument\u002F9731711) — A commercialized processing-in-memory design.\n\n---\n\n## AI Accelerator Architecture\n\nThe chips themselves, organized by class.\n\n### GPUs\n\n- [NVIDIA Hopper Architecture Whitepaper](https:\u002F\u002Fresources.nvidia.com\u002Fen-us-tensor-core) — H100: FP8, the Transformer Engine, and TMA.\n- [NVIDIA Blackwell Architecture](https:\u002F\u002Fwww.nvidia.com\u002Fen-us\u002Fdata-center\u002Ftechnologies\u002Fblackwell-architecture\u002F) — The GB200\u002FB200 generation for trillion-parameter models.\n- [AMD CDNA Architecture](https:\u002F\u002Fwww.amd.com\u002Fen\u002Ftechnologies\u002Fcdna.html) — The compute architecture behind the MI300 series.\n- [Dissecting the Ampere GPU Architecture](https:\u002F\u002Farxiv.org\u002Fabs\u002F2402.13499) — Microbenchmark-driven analysis of modern GPU internals.\n\n### TPUs & Systolic ASICs\n\n- [In-Datacenter Performance Analysis of a TPU (TPUv1)](https:\u002F\u002Farxiv.org\u002Fabs\u002F1704.04760) — Jouppi et al.'s landmark ISCA '17 paper.\n- [A Domain-Specific Supercomputer for Training DNNs (TPUv3\u002Fv4)](https:\u002F\u002Fcacm.acm.org\u002Fmagazines\u002F2020\u002F7\u002F245702-a-domain-specific-supercomputer-for-training-deep-neural-networks\u002Ffulltext) — Google's system-level TPU design.\n- [TPU v4: An Optically Reconfigurable Supercomputer](https:\u002F\u002Farxiv.org\u002Fabs\u002F2304.01433) — Optical circuit switching for large-scale training.\n- [Ten Lessons From Three Generations of TPUs](https:\u002F\u002Fieeexplore.ieee.org\u002Fdocument\u002F9138922) — Jouppi and Patterson on hardware-software co-design.\n\n### NPUs & Edge AI\n\n- [Apple Machine Learning Research](https:\u002F\u002Fmachinelearning.apple.com\u002F) — Publications on the Apple Neural Engine and on-device ML.\n- [Coral \u002F Edge TPU](https:\u002F\u002Fcoral.ai\u002F) — Google's edge inference accelerator.\n- [MLPerf Tiny \u002F TinyML](https:\u002F\u002Fgithub.com\u002Fmlcommons\u002Ftiny) — Benchmarks and models for microcontroller-class inference.\n- [Efficient Deep Learning (MIT 6.5940 \u002F TinyML)](https:\u002F\u002Fefficientml.ai\u002F) — Song Han's course on model compression and edge deployment.\n- [A Survey of Accelerator Architectures for DNNs](https:\u002F\u002Fieeexplore.ieee.org\u002Fdocument\u002F9060877) — Broad coverage of the accelerator design space.\n\n### FPGA & Reconfigurable\n\n- [FINN](https:\u002F\u002Fgithub.com\u002FXilinx\u002Ffinn) — AMD\u002FXilinx's framework for quantized neural network inference on FPGAs.\n- [hls4ml](https:\u002F\u002Fgithub.com\u002Ffastmachinelearning\u002Fhls4ml) — Translating ML models to FPGA firmware via high-level synthesis.\n- [Vitis AI](https:\u002F\u002Fgithub.com\u002FXilinx\u002FVitis-AI) — AMD\u002FXilinx's development stack for FPGA\u002FACAP inference.\n- [Brainwave: A Configurable Cloud-Scale DNN Processor](https:\u002F\u002Fwww.microsoft.com\u002Fen-us\u002Fresearch\u002Fpublication\u002Fserving-dnns-real-time-datacenter-scale-project-brainwave\u002F) — Microsoft's real-time FPGA AI serving.\n\n### RISC-V for AI\n\n- [RISC-V Vector Extension (RVV)](https:\u002F\u002Fgithub.com\u002Friscv\u002Friscv-v-spec) — The vector ISA extension for data-parallel workloads.\n- [RISC-V Specifications](https:\u002F\u002Friscv.org\u002Ftechnical\u002Fspecifications\u002F) — The open ISA underpinning much accelerator research.\n- [Ara](https:\u002F\u002Fgithub.com\u002Fpulp-platform\u002Fara) — A RISC-V vector processor from ETH Zürich's PULP platform.\n\n---\n\n## Simulators & Modeling\n\nTools for exploring the design space before committing to silicon.\n\n- [gem5](https:\u002F\u002Fwww.gem5.org\u002F) — The de facto community architecture simulator.\n- [Accel-Sim](https:\u002F\u002Faccel-sim.github.io\u002F) — A framework for simulating and validating GPU architectures.\n- [GPGPU-Sim](https:\u002F\u002Fgithub.com\u002Fgpgpu-sim\u002Fgpgpu-sim_distribution) — Cycle-level simulation of NVIDIA GPUs running CUDA\u002FOpenCL.\n- [SCALE-Sim](https:\u002F\u002Fgithub.com\u002FARM-software\u002FSCALE-Sim) — ARM's systolic-array CNN accelerator simulator.\n- [Timeloop \u002F Accelergy](https:\u002F\u002Fgithub.com\u002FNVlabs\u002Ftimeloop) — Mapping and energy\u002Farea modeling for DNN accelerators.\n- [Sparseloop](https:\u002F\u002Fgithub.com\u002FAccelergy-Project\u002Fsparseloop) — Analytical modeling for sparse tensor accelerators.\n- [ASTRA-sim](https:\u002F\u002Fgithub.com\u002Fastra-sim\u002Fastra-sim) — Distributed ML training platform and network co-design simulator.\n- [LLMCompass](https:\u002F\u002Fgithub.com\u002FPrincetonUniversity\u002FLLMCompass) — Hardware evaluation for LLM inference.\n- [Roofline: An Insightful Visual Performance Model](https:\u002F\u002Fdl.acm.org\u002Fdoi\u002F10.1145\u002F1498765.1498785) — Williams, Waterman, and Patterson's foundational model.\n\n---\n\n## Chip Design\n\nFollowing the people and publications that explain how chips are actually designed, built, and brought to market — the industry context that connects everything above.\n\n### Blogs & Newsletters\n\n- [SemiAnalysis](https:\u002F\u002Fsemianalysis.com\u002F) — Dylan Patel's deep dives on the semiconductor industry, AI hardware, and the supply chain.\n- [The EDA Primer: From RTL to Silicon](https:\u002F\u002Fnewsletter.semianalysis.com\u002Fp\u002Fthe-eda-primer-from-rtl-to-silicon) — SemiAnalysis's end-to-end walkthrough of the chip design flow; the single best starting point for the big picture.\n\n### YouTube Channels\n\n- [Asianometry](https:\u002F\u002Fwww.youtube.com\u002F@Asianometry) — Accessible, well-researched videos on semiconductor history, manufacturing, and the industry.\n- [CalebWritesCode](https:\u002F\u002Fwww.youtube.com\u002F@CalebWritesCode) — Hands-on GPU programming and low-level systems tutorials.\n- [Dwarkesh Patel](https:\u002F\u002Fwww.youtube.com\u002F@DwarkeshPatel) — Long-form interviews with leading figures in AI and hardware.\n- [3Blue1Brown](https:\u002F\u002Fwww.youtube.com\u002F@3blue1brown) — Grant Sanderson's visual explanations of the math and neural networks behind the workloads.\n\n### Interactive & Visual\n\n- [brrrviz](https:\u002F\u002Fbrrrviz.com\u002F) — An interactive visualization of GPU architecture and how modern GPUs go brrr.\n\n---\n\n## RTL Design\n\nRegister-transfer-level design in Verilog and SystemVerilog — the entry point to any accelerator implementation. Start with the textbook, follow the lectures, then build fluency on the practice sites.\n\n- **Textbook** — [Digital Design and Computer Architecture](https:\u002F\u002Fwww.elsevier.com\u002Fbooks\u002Fdigital-design-and-computer-architecture-risc-v-edition\u002Fharris\u002F978-0-12-820064-3), Harris & Harris. The standard undergraduate text taking you from logic gates to a working RISC-V processor.\n- **Lectures** — [Onur Mutlu — Digital Design & Computer Architecture (ETH Zürich)](https:\u002F\u002Fsafari.ethz.ch\u002Fdigitaltechnik\u002F). A complete, freely recorded lecture series widely regarded as the best online course on the subject.\n- **Practice** — [HDLBits](https:\u002F\u002Fhdlbits.01xz.net\u002F). Interactive Verilog problems with instant feedback; the single most effective way to build RTL coding fluency.\n- **Reference** — [ASIC World](https:\u002F\u002Fwww.asic-world.com\u002Fverilog\u002Fveritut.html). A free, comprehensive Verilog\u002FSystemVerilog tutorial and syntax reference to keep open while you code.\n\n---\n\n## Design Verification\n\nConfirming the RTL does what it should — typically the majority of the effort on a real chip. Learn the methodology from the textbook, then practice UVM on the training sites.\n\n- **Textbook** — [SystemVerilog for Verification](https:\u002F\u002Flink.springer.com\u002Fbook\u002F10.1007\u002F978-1-4614-0715-7), Spear & Tumbush. The definitive introduction to the SystemVerilog features and testbench techniques used in industry.\n- **Lectures & Resources** — [Verification Academy](https:\u002F\u002Fverificationacademy.com\u002F). Siemens EDA's free hub of courses, the canonical UVM Cookbook, and methodology guides — the go-to reference for DV.\n- **Training** — [ChipVerify](https:\u002F\u002Fwww.chipverify.com\u002F). Free, approachable SystemVerilog and UVM tutorials with worked examples, ideal for getting members productive quickly.\n- **Hands-on** — [cocotb](https:\u002F\u002Fwww.cocotb.org\u002F). Write testbenches in Python instead of SystemVerilog; the most accessible on-ramp to writing real verification.\n\n---\n\n## Physical Design\n\nTurning a synthesized netlist into a manufacturable, timing-clean layout (synthesis → floorplan → placement → CTS → routing → timing\u002Fsignoff). Ground yourself in the textbooks, then run a full flow hands-on.\n\n- **Textbook** — [VLSI Physical Design: From Graph Partitioning to Timing Closure](https:\u002F\u002Flink.springer.com\u002Fbook\u002F10.1007\u002F978-90-481-9591-6), Kahng, Lienig, Markov & Hu. The standard text covering every stage of the physical design flow.\n- **Textbook (Circuits)** — [CMOS VLSI Design: A Circuits and Systems Perspective](https:\u002F\u002Fpages.hmc.edu\u002Fharris\u002Fcmosvlsi\u002F4e\u002Findex.html), Weste & Harris. The classic bridge from transistors and layout to full VLSI systems.\n- **Textbook (Timing)** — [Static Timing Analysis for Nanometer Designs](https:\u002F\u002Flink.springer.com\u002Fbook\u002F10.1007\u002F978-0-387-93820-2), Bhasker & Chadha. The definitive reference for understanding timing closure.\n- **Lectures** — [NPTEL — VLSI Physical Design Automation](https:\u002F\u002Fnptel.ac.in\u002Fcourses\u002F106105161). A complete, freely available lecture course on the algorithms behind each PD stage.\n- **Training** — [VLSI System Design (VSD)](https:\u002F\u002Fwww.vlsisystemdesign.com\u002F). Popular hands-on courses and workshops that walk you through a real RTL-to-GDSII flow.\n- **Hands-on** — [OpenLane](https:\u002F\u002Fgithub.com\u002FThe-OpenROAD-Project\u002FOpenLane). An open, automated RTL-to-GDSII flow on the Sky130 PDK — the best way to actually run physical design end-to-end for free.\n\n---\n\n## University Courses\n\nThe best openly available courses across the stack.\n\n- [Stanford CS217 — Hardware Accelerators for ML](https:\u002F\u002Fcs217.stanford.edu\u002F) — Systems and hardware for machine learning.\n- [Stanford CS149 — Parallel Computing](https:\u002F\u002Fgfxcourses.stanford.edu\u002Fcs149) — Kayvon Fatahalian's parallel programming course.\n- [MIT 6.5940 — TinyML & Efficient Deep Learning](https:\u002F\u002Fefficientml.ai\u002F) — Song Han's course on compression, quantization, and acceleration.\n- [MIT 6.172 — Performance Engineering](https:\u002F\u002Focw.mit.edu\u002Fcourses\u002F6-172-performance-engineering-of-software-systems-fall-2018\u002F) — Squeezing performance out of modern hardware.\n- [CMU 15-418 — Parallel Computer Architecture](https:\u002F\u002Fwww.cs.cmu.edu\u002F~418\u002F) — The classic parallelism course.\n- [CMU 10-414\u002F714 — Deep Learning Systems](https:\u002F\u002Fdlsyscourse.org\u002F) — Build a deep learning framework from scratch.\n- [Berkeley CS152\u002F252 — Computer Architecture](https:\u002F\u002Finst.eecs.berkeley.edu\u002F~cs152\u002F) — Krste Asanović's architecture sequence.\n- [ETH Zürich — Digital Design & Computer Architecture](https:\u002F\u002Fsafari.ethz.ch\u002Fdigitaltechnik\u002F) — Onur Mutlu's freely recorded lectures.\n- [UW CSE 599W — Systems for ML](https:\u002F\u002Fdlsys.cs.washington.edu\u002F) — Tianqi Chen's ML systems course.\n\n","这是一个面向AI加速器领域的高质量资源整理清单，系统性汇集了从芯片设计到推理服务的学术论文、开源工具与技术资料。项目覆盖GPU\u002FTPU\u002FNPU等硬件架构、CUDA\u002FTriton等编程框架、FlashAttention\u002FPagedAttention等核心算子，以及量化、KV缓存、MoE等推理优化技术，强调权威性与实用性。适用于AI系统工程师、计算机体系结构研究者及从事大模型部署与硬件协同设计的技术人员快速定位关键参考资料。",2,"2026-07-15 02:30:06","CREATED_QUERY"]