[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"project-84339":3},{"id":4,"name":5,"fullName":6,"owner":7,"repo":5,"description":8,"homepage":9,"htmlUrl":10,"language":11,"languages":9,"totalLinesOfCode":9,"stars":12,"forks":13,"watchers":14,"openIssues":15,"contributorsCount":9,"subscribersCount":16,"size":16,"stars1d":17,"stars7d":17,"stars30d":17,"stars90d":16,"forks30d":16,"starsTrendScore":18,"compositeScore":19,"rankGlobal":9,"rankLanguage":9,"license":9,"archived":20,"fork":20,"defaultBranch":21,"hasWiki":20,"hasPages":20,"topics":9,"createdAt":9,"pushedAt":9,"updatedAt":22,"readmeContent":23,"aiSummary":9,"trendingCount":16,"starSnapshotCount":16,"syncStatus":24,"lastSyncTime":25,"discoverSource":26},84339,"tflite-micro","tensorflow\u002Ftflite-micro","tensorflow","Infrastructure to enable deployment of ML models to low-power resource-constrained embedded targets (including microcontrollers and digital signal processors).",null,"https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro","C++",2948,1047,60,33,0,1,3,31.06,false,"main","2026-06-12 02:04:39","\u003C!--ts-->\n- [TensorFlow Lite for Microcontrollers](#tensorflow-lite-for-microcontrollers)\n- [Build Status](#build-status)\n  - [CI Status](#ci-status)\n  - [Community Supported TFLM Examples](#community-supported-tflm-examples)\n- [Contributing](#contributing)\n- [Getting Help](#getting-help)\n- [Additional Documentation](#additional-documentation)\n- [RFCs](#rfcs)\n\n\u003C!-- Added by: advaitjain, at: Mon 04 Oct 2021 11:23:57 AM PDT -->\n\n\u003C!--te-->\n\n# TensorFlow Lite for Microcontrollers\n\nTensorFlow Lite for Microcontrollers is a port of TensorFlow Lite designed to\nrun machine learning models on DSPs, microcontrollers and other devices with\nlimited memory.\n\nAdditional Links:\n * [Tensorflow github repository](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftensorflow\u002F)\n * [TFLM at tensorflow.org](https:\u002F\u002Fwww.tensorflow.org\u002Flite\u002Fmicrocontrollers)\n\n# Build Status\n\n## CI Status\n| Group | Status |\n| :--- | :--- |\n| Core | [![CI](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_core.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_core.yml) [![CI](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_windows.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_windows.yml)  [![Sync](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Fsync.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Fsync.yml) |\n| Targets | [![Cortex-M](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_cortex_m.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_cortex_m.yml) [![RISC-V](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_riscv.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_riscv.yml) [![Hexagon](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_hexagon.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_hexagon.yml) [![Xtensa](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_xtensa.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Frun_xtensa.yml) |\n| Misc | [![Generate Integration Test](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Fgenerate_integration_tests.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Factions\u002Fworkflows\u002Fgenerate_integration_tests.yml) |\n\n\n## Community Supported TFLM Examples\nThis table captures platforms that TFLM has been ported to. Please see\n[New Platform Support](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Fnew_platform_support.md) for\nadditional documentation.\n\nPlatform      |    Status     |\n-----------     | --------------|\nArduino         | [![Arduino](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro-arduino-examples\u002Factions\u002Fworkflows\u002Fci.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro-arduino-examples\u002Factions\u002Fworkflows\u002Fci.yml) [![Antmicro](https:\u002F\u002Fgithub.com\u002Fantmicro\u002Ftensorflow-arduino-examples\u002Factions\u002Fworkflows\u002Ftest_examples.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Fantmicro\u002Ftensorflow-arduino-examples\u002Factions\u002Fworkflows\u002Ftest_examples.yml) |\n[Coral Dev Board Micro](https:\u002F\u002Fcoral.ai\u002Fproducts\u002Fdev-board-micro) | [TFLM + EdgeTPU Examples for Coral Dev Board Micro](https:\u002F\u002Fgithub.com\u002Fgoogle-coral\u002Fcoralmicro) |\nEspressif Systems Dev Boards  | [![ESP Dev Boards](https:\u002F\u002Fgithub.com\u002Fespressif\u002Ftflite-micro-esp-examples\u002Factions\u002Fworkflows\u002Fci.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Fespressif\u002Ftflite-micro-esp-examples\u002Factions\u002Fworkflows\u002Fci.yml) |\nIngenic MIPS Boards | [![Ingenic MIPS Boards](https:\u002F\u002Fgithub.com\u002Fyinzara\u002Fingenic-tflite-micro\u002Factions\u002Fworkflows\u002Fci.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Fyinzara\u002Fingenic-tflite-micro\u002Ftree\u002Fmain\u002Fexamples\u002Fhello_world) |\nRenesas Boards | [TFLM Examples for Renesas Boards](https:\u002F\u002Fgithub.com\u002Frenesas\u002Ftflite-micro-renesas) |\nSilicon Labs Dev Kits        | [TFLM Examples for Silicon Labs Dev Kits](https:\u002F\u002Fgithub.com\u002FSiliconLabs\u002Ftflite-micro-efr32-examples)\nSparkfun Edge   | [![Sparkfun Edge](https:\u002F\u002Fgithub.com\u002Fadvaitjain\u002Ftflite-micro-sparkfun-edge-examples\u002Factions\u002Fworkflows\u002Fci.yml\u002Fbadge.svg?event=schedule)](https:\u002F\u002Fgithub.com\u002Fadvaitjain\u002Ftflite-micro-sparkfun-edge-examples\u002Factions\u002Fworkflows\u002Fci.yml)\nTexas Instruments Dev Boards | [![Texas Instruments Dev Boards](https:\u002F\u002Fgithub.com\u002FTexasInstruments\u002Ftensorflow-lite-micro-examples\u002Factions\u002Fworkflows\u002Fci.yml\u002Fbadge.svg?event=status)](https:\u002F\u002Fgithub.com\u002FTexasInstruments\u002Ftensorflow-lite-micro-examples\u002Factions\u002Fworkflows\u002Fci.yml)\n\n\n# Contributing\nSee our [contribution documentation](CONTRIBUTING.md).\n\n# Getting Help\n\nA [Github issue](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftflite-micro\u002Fissues\u002Fnew\u002Fchoose)\nshould be the primary method of getting in touch with the TensorFlow Lite Micro\n(TFLM) team.\n\nThe following resources may also be useful:\n\n1.  SIG Micro [email group](https:\u002F\u002Fgroups.google.com\u002Fa\u002Ftensorflow.org\u002Fg\u002Fmicro)\n    and\n    [monthly meetings](http:\u002F\u002Fdoc\u002F1YHq9rmhrOUdcZnrEnVCWvd87s2wQbq4z17HbeRl-DBc).\n\n1.  SIG Micro [gitter chat room](https:\u002F\u002Fgitter.im\u002Ftensorflow\u002Fsig-micro).\n\n1. For questions that are not specific to TFLM, please consult the broader TensorFlow project, e.g.:\n   * Create a topic on the [TensorFlow Discourse forum](https:\u002F\u002Fdiscuss.tensorflow.org)\n   * Send an email to the [TensorFlow Lite mailing list](https:\u002F\u002Fgroups.google.com\u002Fa\u002Ftensorflow.org\u002Fg\u002Ftflite)\n   * Create a [TensorFlow issue](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Ftensorflow\u002Fissues\u002Fnew\u002Fchoose)\n   * Create a [Model Optimization Toolkit](https:\u002F\u002Fgithub.com\u002Ftensorflow\u002Fmodel-optimization) issue\n\n# Additional Documentation\n\n * [Continuous Integration](docs\u002Fcontinuous_integration.md)\n * [Benchmarks](tensorflow\u002Flite\u002Fmicro\u002Fbenchmarks\u002FREADME.md)\n * [Profiling](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Fprofiling.md)\n * [Memory Management](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Fmemory_management.md)\n * [Logging](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Flogging.md)\n * [Porting Reference Kernels from TfLite to TFLM](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Fporting_reference_ops.md)\n * [Optimized Kernel Implementations](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Foptimized_kernel_implementations.md)\n * [New Platform Support](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Fnew_platform_support.md)\n * Platform\u002FIP support\n   * [Arm IP support](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Farm.md)\n * [Software Emulation with Renode](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Frenode.md)\n * [Software Emulation with QEMU](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Fqemu.md)\n * [Compression](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Fcompression.md)\n   * [MNIST Compression Tutorial](tensorflow\u002Flite\u002Fmicro\u002Fcompression\u002Fmnist_compression_tutorial.ipynb)\n * [Python Dev Guide](docs\u002Fpython.md)\n * [Automatically Generated Files](docs\u002Fautomatically_generated_files.md)\n * [Python Interpreter Guide](python\u002Ftflite_micro\u002FREADME.md)\n\n# RFCs\n\n1. [Pre-allocated tensors](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Frfc\u002F001_preallocated_tensors.md)\n1. [TensorFlow Lite for Microcontrollers Port of 16x8 Quantized Operators](tensorflow\u002Flite\u002Fmicro\u002Fdocs\u002Frfc\u002F002_16x8_quantization_port.md)\n",2,"2026-06-11 04:12:51","trending"]