[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"project-77837":3},{"id":4,"name":5,"fullName":6,"owner":7,"repo":5,"description":8,"homepage":9,"htmlUrl":9,"language":10,"languages":9,"totalLinesOfCode":9,"stars":11,"forks":12,"watchers":13,"openIssues":14,"contributorsCount":15,"subscribersCount":15,"size":15,"stars1d":14,"stars7d":12,"stars30d":16,"stars90d":15,"forks30d":15,"starsTrendScore":17,"compositeScore":18,"rankGlobal":9,"rankLanguage":9,"license":19,"archived":20,"fork":20,"defaultBranch":21,"hasWiki":22,"hasPages":20,"topics":23,"createdAt":9,"pushedAt":9,"updatedAt":31,"readmeContent":32,"aiSummary":33,"trendingCount":15,"starSnapshotCount":15,"syncStatus":13,"lastSyncTime":34,"discoverSource":35},77837,"verilog-generator","Eriemon\u002Fverilog-generator","Eriemon","Agent skill for Verilog-2001 RTL generation and FPGA design workflows.",null,"Python",165,5,2,4,0,182,12,2.33,"Apache License 2.0",false,"main",true,[24,25,26,27,28,29,30],"agent-skill","codex-skill","eda","fpga","hardware-generation","rtl","verilog","2026-06-12 02:03:45","\u003Cp align=\"center\">\n  \u003Ca href=\"README.md\">\u003Cstrong>English\u003C\u002Fstrong>\u003C\u002Fa>\n  \u003Cspan> | \u003C\u002Fspan>\n  \u003Ca href=\"README-CN.md\">中文\u003C\u002Fa>\n\u003C\u002Fp>\n\n\u003Cp align=\"center\">\n  \u003Cimg src=\"docs\u002Fassets\u002Fhero.svg\" alt=\"Verilog Generator\" width=\"100%\">\n\u003C\u002Fp>\n\n\u003Cp align=\"center\">\n  \u003Ca href=\"LICENSE\">\u003Cimg alt=\"License\" src=\"https:\u002F\u002Fimg.shields.io\u002Fbadge\u002Flicense-Apache--2.0-1f6feb\">\u003C\u002Fa>\n  \u003Ca href=\"pyproject.toml\">\u003Cimg alt=\"Python\" src=\"https:\u002F\u002Fimg.shields.io\u002Fbadge\u002Fpython-3.10%2B-2f81f7\">\u003C\u002Fa>\n  \u003Cimg alt=\"Version\" src=\"https:\u002F\u002Fimg.shields.io\u002Fbadge\u002Fversion-v0.2.1-7c3aed\">\n  \u003Ca href=\"SKILL.md\">\u003Cimg alt=\"Agent Skill\" src=\"https:\u002F\u002Fimg.shields.io\u002Fbadge\u002Fagent-skill-16a34a\">\u003C\u002Fa>\n  \u003Ca href=\"ENGINEERING_DESIGN_GOALS.md\">\u003Cimg alt=\"Target\" src=\"https:\u002F\u002Fimg.shields.io\u002Fbadge\u002Ftarget-Verilog--2001-f59e0b\">\u003C\u002Fa>\n\u003C\u002Fp>\n\n\u003Ch1 align=\"center\">Verilog Generator\u003C\u002Fh1>\n\n\u003Cp align=\"center\">\n  A Codex-ready agent skill for disciplined Verilog-2001 RTL workflows.\n\u003C\u002Fp>\n\nVerilog Generator turns an AI coding agent into a more reliable RTL engineering assistant. It provides trigger metadata, workflow instructions, interface templates, deterministic runtime helpers, examples, and validation gates for moving from confirmed hardware intent to synthesizable Verilog and self-checking testbenches.\n\nThis repository is primarily an **agent skill package**. The Python CLI is included as the deterministic execution layer, but the main interface is the skill surface an agent can load and follow.\n\n## Why It Exists\n\nRTL work needs precision before code. Verilog Generator makes the agent confirm module names, ports, clock\u002Freset behavior, pipeline expectations, interface family, reference behavior, and verification cases before producing artifacts.\n\nUse it when an agent needs to work on:\n\n- Synthesizable Verilog-2001 RTL modules.\n- Self-checking Verilog testbenches.\n- Python reference contracts for semantic comparison.\n- AXI-Stream, AXI4-Lite, AXI4, AHB, APB, native, or custom interface shapes.\n- Static validation, simulator readiness, workflow traces, and generated artifact review.\n\n## Skill Architecture\n\n\u003Cp align=\"center\">\n  \u003Cimg src=\"docs\u002Fassets\u002Farchitecture.svg\" alt=\"Verilog Generator skill architecture\" width=\"100%\">\n\u003C\u002Fp>\n\n## Workflow\n\n\u003Cp align=\"center\">\n  \u003Cimg src=\"docs\u002Fassets\u002Fworkflow.svg\" alt=\"Verilog Generator workflow\" width=\"100%\">\n\u003C\u002Fp>\n\n## Repository Map\n\n| Path | Purpose |\n| --- | --- |\n| `SKILL.md` | Agent-facing routing, workflow, constraints, and tool usage rules. |\n| `agents\u002Fopenai.yaml` | UI metadata for skill lists and invocation chips. |\n| `runtime\u002Fverilog_generator\u002F` | Deterministic scaffolding, prompt rendering, extraction, validation, traces, and workflow state. |\n| `integration\u002Fverilog_adapter.py` | Stable host-facing facade for workflow, prompt, and validation calls. |\n| `assets\u002Finterface_templates\u002F` | Reusable AXI-Stream, AXI4-Lite, AXI4, AHB, and APB interface patterns. |\n| `assets\u002Frefined_verilog_templates\u002F` | Reusable refined RTL shell snippets and grouped-port patterns. |\n| `assets\u002Fuse_case_templates\u002F` | Packaged JESD, SPI, and mixed-signal reference templates with RTL, Tcl, and constraint skeletons. |\n| `assets\u002Fexamples\u002F` | Example specs, remote fixtures, and refined template inputs for validation and regression checks. |\n| `evals\u002F` | Repo-local skill-effectiveness cases for workflow and remote-validation regressions. |\n| `RELEASE_RECEIPT.json` | Provenance record for the imported `v0.2.1` release package. |\n\n## Quick Start\n\nTell your AI assistant: install https:\u002F\u002Fgithub.com\u002FEriemon\u002Fverilog-generator\n\nPlace this repository in a Codex skill search path to use it as an agent skill. For runtime development and local checks:\n\n```powershell\npython -m runtime.verilog_generator --version\npython -m runtime.verilog_generator scaffold --name rtl_adapter --out .\\reports\\verilog\\spec.json\npython -m runtime.verilog_generator prompt --spec .\\reports\\verilog\\spec.json --out .\\reports\\verilog\\prompt.md\n```\n\nStatic validation without external HDL tools:\n\n```powershell\npython -m runtime.verilog_generator validate --spec .\\reports\\verilog\\spec.json --path .\\reports\\verilog\\generated --no-external\n```\n\nExternal validation requires real HDL tools. This project does not claim Vivado\u002Fxsim, VCS, iverilog, or yosys acceptance unless those tools actually run.\n\nThe `v0.2.1` update adds a Verilog comment-placement contract and validator, then wires comment checks into validation, static lint, prompt rendering, CLI behavior, semantic testbench comments, and smoke coverage.\n\n## Integration API\n\n```python\nfrom integration.verilog_adapter import (\n    render_verilog_prompt,\n    run_verilog_workflow,\n    validate_verilog_artifacts,\n)\n```\n\n- `run_verilog_workflow(...)`: run or resume the staged RTL workflow.\n- `render_verilog_prompt(...)`: render prompts when a host owns the model call.\n- `validate_verilog_artifacts(...)`: validate generated RTL before downstream use.\n\n## Scope\n\nVerilog Generator is intentionally narrow:\n\n- It generates Verilog-2001 `.v` artifacts and self-checking Verilog testbenches.\n- It does not generate HLS, C\u002FC++ kernels, or alternate RTL dialects.\n- It prefers explicit logic over Verilog `function` and `task` blocks for easier waveform debugging.\n- Local secrets, proprietary hardware designs, generated caches, and private remote-server details should stay out of the repository.\n\n## Affiliation\n\nJiyuan Liu and He Li are with the School of Electronic Science and Engineering, Southeast University.\nThey are affiliated with the Heterogeneous Intelligence and Quantum Computing Laboratory (HIQC), which works on heterogeneous intelligence, quantum computing, and related computing systems research.\n\n## Contact\n\nFor questions, collaboration, or academic use, contact: [erie@seu.edu.cn](mailto:erie@seu.edu.cn).\n\n## Citation\n\nThis skill is maintained by authors from the Heterogeneous Intelligence and Quantum Computing Laboratory(HIQC), School of Electronic Science and Engineering, Southeast University.\n\nIf this skill helps your research, teaching, or engineering workflow, please cite it. The canonical citation metadata is maintained in [CITATION.cff](CITATION.cff).\n\n```bibtex\n@software{liu_2026_verilog_generator,\n  author       = {Jiyuan Liu and He Li},\n  title        = {{Verilog Generator}: An Agent Skill for Verilog-2001 RTL Workflows},\n  year         = {2026},\n  version      = {0.2.1},\n  date         = {2026-05-21},\n  url          = {https:\u002F\u002Fgithub.com\u002FEriemon\u002Fverilog-generator},\n  license      = {Apache-2.0},\n  note         = {Agent skill package for disciplined Verilog-2001 RTL workflows}\n}\n```\n\n## License\n\nApache License 2.0. See [LICENSE](LICENSE).\n","Verilog Generator 是一个用于生成Verilog-2001 RTL代码的工作流代理技能。该项目通过提供触发元数据、工作流指令、接口模板、确定性运行时辅助工具、示例及验证门，帮助从确认的硬件意图过渡到可综合的Verilog代码和自检测试平台，从而将AI编码代理转变为更可靠的RTL工程助手。其核心技术特点包括支持多种标准接口（如AXI-Stream, AXI4-Lite等）以及自定义接口形状，并且强调在编写代码前确保模块名称、端口定义、时钟复位行为等方面的准确性。适用于需要精确控制与高质量输出的数字电路设计场景，特别是当涉及到复杂接口设计或希望利用自动化手段提高开发效率时。","2026-06-11 03:56:10","CREATED_QUERY"]