[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"project-2285":3},{"id":4,"name":5,"fullName":6,"owner":7,"repo":5,"description":8,"homepage":9,"htmlUrl":10,"language":11,"languages":10,"totalLinesOfCode":10,"stars":12,"forks":13,"watchers":14,"openIssues":15,"contributorsCount":16,"subscribersCount":16,"size":16,"stars1d":15,"stars7d":17,"stars30d":13,"stars90d":16,"forks30d":16,"starsTrendScore":17,"compositeScore":18,"rankGlobal":10,"rankLanguage":10,"license":19,"archived":20,"fork":20,"defaultBranch":21,"hasWiki":20,"hasPages":20,"topics":22,"createdAt":10,"pushedAt":10,"updatedAt":23,"readmeContent":24,"aiSummary":25,"trendingCount":16,"starSnapshotCount":16,"syncStatus":26,"lastSyncTime":27,"discoverSource":28},2285,"digital-chip-design-agents","chuanseng-ng\u002Fdigital-chip-design-agents","chuanseng-ng","Digital HDL Design Full-stack Agents","",null,"Python",147,41,1,3,0,9,4.87,"MIT License",false,"master",[],"2026-06-12 02:00:39","# digital-chip-design-agents\n\n> Claude Code marketplace plugin — full digital chip design pipeline.  \n> 15 plugins · 16 skill files · 13 chip-design domains + infrastructure + pipeline orchestrator · closed-loop verification↔RTL feedback.\n\n[![Validate](https:\u002F\u002Fgithub.com\u002Fchuanseng-ng\u002Fdigital-chip-design-agents\u002Factions\u002Fworkflows\u002Fvalidate.yml\u002Fbadge.svg)](https:\u002F\u002Fgithub.com\u002Fchuanseng-ng\u002Fdigital-chip-design-agents\u002Factions\u002Fworkflows\u002Fvalidate.yml)\n\n---\n\n## Install\n\n### Option A — Install script (recommended)\n\nClone the repo and run one script — all 15 plugins are installed and enabled in a\nsingle step, no repeated commands needed.\n\n**macOS \u002F Linux \u002F Git Bash:**\n```bash\ngit clone https:\u002F\u002Fgithub.com\u002Fchuanseng-ng\u002Fdigital-chip-design-agents.git\ncd digital-chip-design-agents\nbash install.sh\n```\n\n**Windows (PowerShell):**\n```powershell\ngit clone https:\u002F\u002Fgithub.com\u002Fchuanseng-ng\u002Fdigital-chip-design-agents.git\ncd digital-chip-design-agents\n.\\install.ps1\n```\n\nRestart Claude Code after running — all 16 skills and 15 agents will be active.\n\n### Option B — Marketplace (selective install)\n\nIf you only need specific domains, install them individually via the Claude Code\nmarketplace. First register the marketplace, then install the domains you need:\n\n```text\n\u002Fplugin marketplace add github:chuanseng-ng\u002Fdigital-chip-design-agents\n```\n\n\u003Cdetails>\n\u003Csummary>Individual plugin install commands (click to expand)\u003C\u002Fsummary>\n\n```text\n\u002Fplugin install chip-design-architecture@digital-chip-design-agents\n\u002Fplugin install chip-design-rtl@digital-chip-design-agents\n\u002Fplugin install chip-design-verification@digital-chip-design-agents\n\u002Fplugin install chip-design-formal@digital-chip-design-agents\n\u002Fplugin install chip-design-synthesis@digital-chip-design-agents\n\u002Fplugin install chip-design-dft@digital-chip-design-agents\n\u002Fplugin install chip-design-sta@digital-chip-design-agents\n\u002Fplugin install chip-design-hls@digital-chip-design-agents\n\u002Fplugin install chip-design-pd@digital-chip-design-agents\n\u002Fplugin install chip-design-soc@digital-chip-design-agents\n\u002Fplugin install chip-design-compiler@digital-chip-design-agents\n\u002Fplugin install chip-design-firmware@digital-chip-design-agents\n\u002Fplugin install chip-design-fpga@digital-chip-design-agents\n```\n\n\u003C\u002Fdetails>\n\n### Option C — Other AI assistants (Copilot \u002F Gemini \u002F OpenCode \u002F Codex CLI)\n\nRun the install script from your chip design project directory with `--ide`:\n\n```bash\n# GitHub Copilot — creates .github\u002Finstructions\u002F in your project\nbash \u002Fpath\u002Fto\u002Fdigital-chip-design-agents\u002Finstall.sh --ide copilot\n# Commit the generated .github\u002F files to share rules with your team.\n\n# Gemini Code Assist — creates GEMINI.md in your project (or ~\u002FGEMINI.md with --global)\nbash \u002Fpath\u002Fto\u002Fdigital-chip-design-agents\u002Finstall.sh --ide gemini\n\n# OpenCode — creates opencode.json in your project; use \u002Fmode chip-\u003Cdomain> to activate\nbash \u002Fpath\u002Fto\u002Fdigital-chip-design-agents\u002Finstall.sh --ide opencode\n\n# OpenAI Codex CLI — creates AGENTS.md in your project (or ~\u002F.codex\u002Finstructions.md with --global)\nbash \u002Fpath\u002Fto\u002Fdigital-chip-design-agents\u002Finstall.sh --ide codex\n\n# All IDEs at once (also installs Claude Code)\nbash \u002Fpath\u002Fto\u002Fdigital-chip-design-agents\u002Finstall.sh --ide all\n```\n\n**Windows (PowerShell):** replace `bash install.sh` with `.\\install.ps1` and `--ide` with `-IDE`.\n\nDomain knowledge is loaded directly from the plugin source files — no duplicate content.\nRe-run the install command to pick up any future updates.\n\n---\n\n### Usage — describe your task in natural language\n\n```\nRun the RTL design flow for my AXI DMA controller block\nAnalyse timing violations on this routed DEF and suggest ECOs\nGenerate ATPG patterns for this DFT-inserted netlist\nBuild a UVM testbench for my FIFO block\n```\n\nClaude automatically loads the correct skill before executing.\n\n---\n\n## Available Plugins\n\n| Plugin Name | Domain | Invoke When You Want To... |\n|-------------|--------|---------------------------|\n| `chip-design-architecture` | Architecture Evaluation | Explore microarch candidates, estimate PPA, assess risk |\n| `chip-design-rtl` | RTL Design (SystemVerilog) | Write, lint, CDC-check, or synthesis-check RTL |\n| `chip-design-verification` | Functional Verification (UVM) | Build testbench, write tests, close coverage, run regression |\n| `chip-design-formal` | Formal Verification (FPV\u002FLEC) | Prove properties, check equivalence, close formal gaps |\n| `chip-design-synthesis` | Logic Synthesis | Set up SDC, run synthesis, verify netlist with LEC |\n| `chip-design-dft` | Design for Test | Plan DFT, insert scan, run ATPG, set up JTAG |\n| `chip-design-sta` | Static Timing Analysis | Analyse timing, guide ECO closure, sign off timing |\n| `chip-design-hls` | High-Level Synthesis | Convert C\u002FC++ to RTL, optimise directives, co-simulate |\n| `chip-design-pd` | Physical Design | Full PD flow: floorplan → placement → CTS → routing → sign-off |\n| `chip-design-soc` | SoC IP Integration | Qualify IPs, configure bus fabric, run chip-level sim |\n| `chip-design-compiler` | Compiler Toolchain | Build LLVM\u002FGCC backend, assembler, linker, runtime for custom ISA |\n| `chip-design-firmware` | Embedded Firmware | BSP, HAL drivers, RTOS integration, firmware validation |\n| `chip-design-fpga` | FPGA Emulation | Port ASIC to FPGA, bring up hardware, validate SW on prototype |\n| `chip-design-infrastructure` | Infrastructure & Memory | Detect EDA tools, deploy wrappers, configure MCP servers, distil domain memory |\n| `chip-design-meta` | Pipeline Orchestration | Drive closed-loop verification↔RTL feedback, manage fix_requests, enforce iteration cap |\n\n---\n\n## How It Works\n\nEach plugin installs two things:\n\n1. **A Skill** (`plugins\u002F\u003Cdomain>\u002Fskills\u002F\u003Cdomain>\u002FSKILL.md`) — domain knowledge Claude reads\n   before executing. Contains stage-by-stage rules, QoR metrics, common fixes, and output\n   requirements.\n\n2. **An Orchestrator Agent** (`plugins\u002F\u003Cdomain>\u002Fagents\u002F\u003Cdomain>-orchestrator.md`) — a subagent\n   that manages the full multi-stage flow. It sequences stages, enforces pass\u002Ffail criteria,\n   applies loop-back rules when a stage fails, and escalates clearly when human input is needed.\n\nSkills are loaded autonomously by Claude when you describe a task. Orchestrators are\ninvoked explicitly when you want to run a complete flow end-to-end.\n\n---\n\n## Orchestrator Flows\n\nEach orchestrator enforces a strict stage sequence with loop-back rules:\n\n**Physical Design** (example):\n```\nfloorplan → placement → CTS → routing →\ntiming_opt → power_opt → area_opt → signoff\n```\nIf routing DRC fails → retry routing (max 3×).  \nIf signoff timing fails → loop back to timing_opt (max 2×).  \nIf any loop exceeds its limit → escalate to you with full state + recommendations.\n\nAll 13 domain orchestrators follow the same pattern with domain-specific stages and criteria.\n\n---\n\n## Repo Structure\n\n```\ndigital-chip-design-agents\u002F\n│\n├── .claude-plugin\u002F\n│   └── marketplace.json         ← Marketplace registry (all 15 plugins)\n│\n├── plugins\u002F                     ← One isolated directory per plugin\n│   ├── architecture\u002F\n│   │   ├── .claude-plugin\u002F\n│   │   │   └── plugin.json      ← Per-plugin manifest\n│   │   ├── agents\u002F\n│   │   │   └── architecture-orchestrator.md\n│   │   └── skills\u002F\n│   │       └── architecture\u002F\n│   │           └── SKILL.md\n│   ├── rtl-design\u002F\n│   │   ├── .claude-plugin\u002Fplugin.json\n│   │   ├── agents\u002Frtl-design-orchestrator.md\n│   │   └── skills\u002Frtl-design\u002FSKILL.md\n│   ├── ... (13 domain plugins, same layout each)\n│   ├── infrastructure\u002F\n│   │   ├── .claude-plugin\u002Fplugin.json\n│   │   ├── agents\u002Finfrastructure-orchestrator.md\n│   │   ├── skills\u002Finfrastructure\u002FSKILL.md\n│   │   ├── skills\u002Fmemory-keeper\u002F   ← distils experiences.jsonl → knowledge.md\n│   │   │   ├── SKILL.md\n│   │   │   └── distill.py\n│   │   └── tools\u002F                  ← EDA wrapper scripts and MCP adapters\n│   └── meta\u002F                       ← Cross-domain pipeline orchestrator\n│       ├── .claude-plugin\u002Fplugin.json\n│       ├── agents\u002Fpipeline-orchestrator.md\n│       └── skills\u002Fpipeline-orchestration\u002FSKILL.md\n│\n├── ides\u002F                        ← IDE-specific config files (non-Claude)\n│   ├── copilot\u002F\n│   │   ├── .github\u002F\n│   │   │   └── copilot-instructions.md   ← global Copilot workspace instructions\n│   │   └── applyto-map.json     ← domain → file-glob mapping for per-domain rules\n│   ├── gemini\u002F\n│   │   └── gemini-header.md     ← preamble injected into generated GEMINI.md\n│   ├── opencode\u002F\n│   │   └── opencode-base.json   ← base OpenCode config template\n│   └── codex\u002F\n│       └── AGENTS.md            ← preamble injected into generated AGENTS.md (Codex CLI)\n│\n├── memory\u002F                      ← Persistent two-tier memory (per domain)\n│   ├── \u003Cdomain>\u002Fknowledge.md   ← Tier 2: distilled summaries (read at session start)\n│   └── \u003Cdomain>\u002Fexperiences.jsonl ← Tier 1: append-only run records\n│\n├── tools\u002F\n│   └── qor_trends.py           ← QoR metric trending and regression detection\n│\n└── .github\u002F\n    └── workflows\u002F\n        ├── validate.yml         ← CI: validates all files on every PR\n        └── release.yml          ← CD: tags and publishes releases\n```\n\n---\n\n## End-to-End Pipeline\n\nThe 13 design domains (+ the meta pipeline orchestrator) map to a complete chip design pipeline:\n\n```\n[Specification]\n      │\n      ▼\n[1. Architecture Evaluation] ──► microarch doc\n      │\n      ├──► [2. RTL Design]  ──► [3. HLS] (algorithm blocks)\n      │           │\n      │           │           ├──► [4. Functional Verification] ◄──┐\n      │           └──► [5. Formal Verification]    ◄──┤\n      │                       │ (bug found)           │ fix_request loop\n      │                       │                    [Meta \u002F Pipeline Orch.]\n      │                       ▼                       │\n      │              [6. Logic Synthesis]          ────┘\n      │                       │\n      │           ┌───────────┼───────────┐\n      │           ▼           ▼           ▼\n      │      [7. DFT]  [8. Physical  [9. STA]\n      │                   Design]\n      │                       │\n      │                   [Tape-out]\n      │\n      ├──► [10. SoC IP Integration]  (if SoC-level work)\n      ├──► [11. Compiler Toolchain]  (if custom CPU)\n      ├──► [12. Embedded Firmware]\n      └──► [13. FPGA Emulation]      (pre-silicon SW dev)\n```\n\n---\n\n## Memory System\n\nEach domain orchestrator reads from and writes to a two-tier persistent memory store under `memory\u002F`:\n\n- **`memory\u002F\u003Cdomain>\u002Fknowledge.md`** — distilled summaries: known failure patterns, successful tool flags, PDK quirks. Read by every orchestrator at session start.\n- **`memory\u002F\u003Cdomain>\u002Fexperiences.jsonl`** — append-only run records written after every signoff or escalation.\n\n### Distilling new knowledge\n\nAfter enough runs accumulate (default threshold: 5 records), merge new learnings back into `knowledge.md`:\n\n```text\n\u002Fchip-design-infrastructure:memory-keeper --domain synthesis\n\u002Fchip-design-infrastructure:memory-keeper --all --min-records 10\n```\n\nThe `memory-keeper` skill reads the JSONL records, identifies new issue\u002Ffix patterns and tool flags not already captured, and updates the relevant sections of `knowledge.md` without discarding still-valid content.\n\n### QoR trend analysis\n\nTrack how key metrics evolve across runs for a named design:\n\n```bash\n# Text table for all domains where design \"aes_core\" appears\npython3 tools\u002Fqor_trends.py --design aes_core\n\n# WNS trend for synthesis only, with regression alerts\npython3 tools\u002Fqor_trends.py --design aes_core --domain synthesis --metric wns_ns\n\n# Save a matplotlib chart\npython3 tools\u002Fqor_trends.py --design aes_core --plot --output aes_core_qor.png\n\n# Compare area\u002Ftiming across sky130 vs gf180mcu\npython3 tools\u002Fqor_trends.py --design aes_core --domain synthesis --group-by pdk\n\n# Compare Yosys vs DC for the same design on sky130, with a grouped chart\npython3 tools\u002Fqor_trends.py --design aes_core --pdk sky130 --group-by tool --plot\n```\n\nRegression alerts fire automatically when a metric moves in the wrong direction between runs (e.g. WNS degrades, coverage drops).\n\n---\n\n## Contributing\n\nSee [CONTRIBUTING.md](CONTRIBUTING.md). PRs welcome for:\n- Improved domain rules or QoR metrics in any SKILL.md\n- New loop-back rules in orchestrators\n- New skill domains (e.g., package\u002Fassembly, analog integration)\n\nCI validates all files on every PR — the validate workflow must pass before merge.\n\n### Shared metadata in plugin.json\n\nEach `plugins\u002F\u003Cdomain>\u002F.claude-plugin\u002Fplugin.json` repeats the same `author`,\n`homepage`, `repository`, and `license` fields. These are intentional — the\nplugin installer reads each manifest in isolation and requires these fields to\nbe present. The canonical values are:\n\n```json\n\"author\":     { \"name\": \"chuanseng-ng\", \"url\": \"https:\u002F\u002Fgithub.com\u002Fchuanseng-ng\" },\n\"homepage\":   \"https:\u002F\u002Fgithub.com\u002Fchuanseng-ng\u002Fdigital-chip-design-agents\",\n\"repository\": \"https:\u002F\u002Fgithub.com\u002Fchuanseng-ng\u002Fdigital-chip-design-agents\",\n\"license\":    \"MIT\"\n```\n\nWhen updating these fields, change all 14 `plugin.json` files and\n`.claude-plugin\u002Fmarketplace.json` together.\n\n---\n\n## License\n\nMIT — see [LICENSE](LICENSE).\n","该项目提供了一整套数字芯片设计的全栈代理工具，支持从架构设计到验证的全流程。它包含15个插件和16个技能文件，覆盖了13个芯片设计领域，并且具备基础设施管理和流水线编排功能。项目采用Python语言编写，通过闭环保证验证与RTL反馈之间的高效互动。适用于需要自动化和集成化解决方案的数字芯片设计场景，能够显著提高开发效率和设计质量。无论是初学者还是经验丰富的工程师，都可以根据需求选择合适的安装方式来快速上手使用。",2,"2026-06-11 02:49:17","CREATED_QUERY"]